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Version 1.22 of 26th September 2016
- [FW-322] Bug-Fix: Sequence-Replay: a few little segments and a special trigger frequency replay additional segments after the last one
- [FW-267] Bug-Fix: 66xx seq-repl: first step with value one is replayed twice
- [FW-210] Bug-Fix: Output samples missing at the very last block using sequence mode
- [FW-278] New Feature: Add digital output option for X0..X2 lines for M4i.66xx series
- [FW-330] Improvement: Allow output of system clock (divided sample clock) for multi-purpose I/O lines
- [FW-258] Improvement: Add PXIe support to base logic
- [FW-323] Improvement: Improve timing accuracy of trigger and armed output of X0, X1, X2 lines
- [FW-320] Improvement: Change burst write rate for on-board memory to beyond resonance frequency of 22kHz of some power PI filters
- [FW-276] Improvement: Better logic optimization due to different trigger mode encoding
- [FW-212] Bug-Fix: Read out sequence step between card start and first trigger is the last one from previous replay