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Version 1.28 of 18th November 2016
- [FW-222] Bug-Fix: M4i: Sync trigger jitter and wrong position with starhub mounted on Base with PCB V1.0
- [FW-227] Trigger accuracy improvement
- [FW-258] New Feature: Add PXIe support to base logic
- [FW-273] Bug-Fix: Skew between channels of synchronized M4.22xx cards varied from one reset to another
- [FW-320] Improvement: Change burst write rate for on-board memory to beyond resonance frequency of 22kHz of some power PI filters
- [FW-330] Improvement: Allow output of system clock (divided sample clock) for multi-purpose I/O lines
- [FW-335] Bug-Fix: sometimes card didn't respond after PCIe hot reset due to lock of FPGA
- [FW-337] Internal timing improvements
- [FW-354] Bug-Fix: X0/X1/X2 status output not working properly with enabled oversampling
- [FW-352] Bug-Fix: Gated Sampling not working properly since [FW-258]
- [FW-350] Bug-Fix: Timestamps of Gate End and Next Gate start are sometimes identical
- [FW-351] Bug-Fix: No gate end timestamp generated if acquisition ends befoe gate ends
- [FW-349] Bug-Fix: Sometimes incorrect timestampsy